Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING Especificaciones Pagina 1

Busca en linea o descarga Especificaciones para Los conmutadores de red Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING. Vivanco 10-100MB FAST ETHERNET SWITCH 5 PORTS - PROGRAMMING Specifications Manual de usuario

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DP83848C
,
DP83848I
DP83848VYB, DP83848YB
SNLS266E MAY 2007REVISED MARCH 2015
DP83848C/I/VYB/YB PHYTER™ QFP Single Port 10/100 Mb/s Ethernet
Physical Layer Transceiver
1 Introduction
1.1 Features
1
Multiple Temperature Range from –40°C to 105°C IEEE 802.3 ENDEC, 10BASE-T Transceivers and
Filters
Low-Power 3.3-V, 0.18-µm CMOS Technology
IEEE 802.3 PCS, 100BASE-TX Transceivers and
Low-Power Consumption < 270 mW Typical
Filters
3.3-V MAC Interface
IEEE 1149.1 JTAG
Auto-MDIX for 10/100 Mb/s
Integrated ANSI X3.263 Compliant TP-PMD
Energy Detection Mode
Physical Sub-Layer with Adaptive Equalization and
25-MHz Clock Output
Baseline Wander Compensation
SNI Interface (Configurable)
Error-Free Operation up to 150 Meters
RMII Rev. 1.2 Interface (Configurable)
Programmable LED Support for Link, 10/100 Mb/s
MII Serial Management Interface (MDC and MDIO)
Mode, Activity, Duplex and Collision Detect
IEEE 802.3 MII
Single Register Access for Complete PHY Status
IEEE 802.3 Auto-Negotiation and Parallel
10/100 Mb/s Packet BIST (Built in Self Test)
Detection
1.2 Applications
Automotive/Transportation General Embedded Applications
Industrial Controls and Factory Automation
1.3 Description
The number of applications requiring Ethernet connectivity continues to increase, driving Ethernet enabled
devices into harsher environments.
The DP83848C/I/VYB/YB was designed to meet the challenge of these new applications with an extended
temperature performance that goes beyond the typical Industrial temperature range. The
DP83848C/I/VYB/YB is a highly reliable, feature rich, robust device which meets IEEE 802.3 standards
over multiple temperature ranges from commercial to extreme temperatures. This device is ideally suited
for harsh environments such as wireless remote base stations, automotive/transportation, and industrial
control applications.
It offers enhanced ESD protection and the choice of an MII or RMII interface for maximum flexibility in
MPU selection; all in a 48 pin package.
The DP83848VYB extends the leadership position of the PHYTER™ family of devices with a wide
operating temperature range. The TI line of PHYTER transceivers builds on decades of Ethernet expertise
to offer the high performance and flexibility that allows the end user an easy implementation tailored to
meet these application needs.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DP83848VYB/YB HLQFP (48)
7.00 mm × 7.00 mm
DP83848I/C LQFP (48)
(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Indice de contenidos

Pagina 1 - Physical Layer Transceiver

ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityDP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISE

Pagina 2 - 1.4 Functional Block Diagram

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comSIGNAL NAME TYPE PIN # DESCRIPTIONRD-, RD+ I/O 13 Differential re

Pagina 3

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20155 Specifications5.1 Absolute Maximum Ratings(1)(2)MIN MAX UNITSup

Pagina 4 - 3 Device Comparison

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com5.5 DC SpecificationsPINPARAMETER TEST CONDITIONS MIN TYP MAX UNI

Pagina 5 - 4.1 Pin Layout

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20155.6 AC Timing RequirementsPARAMETER DESCRIPTION NOTES MIN TYP MAX

Pagina 6 - 4.4 Mac Data Interface

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comAC Timing Requirements (continued)PARAMETER DESCRIPTION NOTES MIN

Pagina 7 - 4.5 Clock Interface

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015AC Timing Requirements (continued)PARAMETER DESCRIPTION NOTES MIN

Pagina 8 - 4.9 Strap Options

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comAC Timing Requirements (continued)PARAMETER DESCRIPTION NOTES MIN

Pagina 9

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Figure 5-1. Power-Up TimingFigure 5-2. Reset TimingCopyright © 20

Pagina 10 - 4.12 Power Supply Pins

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 5-3. MII Serial Management TimingFigure 5-4. 100 Mb/s MII

Pagina 11 - 5 Specifications

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Figure 5-7. 100BASE-TX Transmit Packet Deassertion TimingFigure 5

Pagina 12 - 5.5 DC Specifications

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com1.4 Functional Block Diagram2 Introduction Copyright © 2007–2015,

Pagina 13 - 5.6 AC Timing Requirements

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 5-10. 100BASE-TX Receive Packet Deassertion TimingFigure 5

Pagina 14 - DP83848VYB, DP83848YB

T2.17.1T2.17.2T2.17.31 0 1 0 1 0 1 0 1 0 1 11st SFD Bit Decoded0000 Preamble SFD DataRXD[3:0]RX_DVRX_CLKCRSTPRDrT2.15.1T2.15.2TX_CLKTX_ENTXDPMD Output

Pagina 15

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 5-19. 10 Mb/s Heartbeat TimingFigure 5-20. 10 Mb/s Jabber

Pagina 16

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Figure 5-24. 100 Mb/s Internal Loopback TimingFigure 5-25. 10 Mb/

Pagina 17 - Submit Documentation Feedback

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 5-26. RMII Transmit TimingFigure 5-27. RMII Receive Timing

Pagina 18

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Figure 5-30. 100 Mb/s X1 to TX_CLK TimingCopyright © 2007–2015, T

Pagina 19 - Specifications 19

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6 Detailed Description6.1 OverviewThe device is 10/100 Mbps Ether

Pagina 20

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.2 Functional Block DiagramCopyright © 2007–2015, Texas Instrume

Pagina 21 - Specifications 21

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.3 Feature DescriptionThis section includes information on the v

Pagina 22

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.3.1.2 Auto-Negotiation Register ControlWhen Auto-Negotiation is

Pagina 23 - Specifications 23

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table of Contents1 Introduction ...

Pagina 24

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comIf the DP83848VYB completes Auto-Negotiation as a result of Paral

Pagina 25

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-2. LED Mode SelectionLED_CFG[1] (bit LED_CFG[0] (bit 5)Mo

Pagina 26 - 6 Detailed Description

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 6-1. AN Strapping and LED Loading Example6.3.3.2 LED Direc

Pagina 27 - 6.2 Functional Block Diagram

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.3.6 Energy Detect ModeWhen Energy Detect is enabled and there i

Pagina 28 - 6.3.1 Auto-Negotiation

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comIf a collision occurs during a receive operation, it is immediate

Pagina 29 - Detailed Description 29

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-3. Supported Packet Sizes at ±50ppm ±100ppm For Each Cloc

Pagina 30 - 6.3.3 LED Interface

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 6-2. Typical MDC/MDIO Read OperationFigure 6-3. Typical MD

Pagina 31

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-5. PHY Address MappingPin # PHYAD Function RXD Function42

Pagina 32 - 6.3.5 BIST

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.4.6 Half Duplex vs. Full DuplexThe DP83848VYB supports both hal

Pagina 33 - 6.4.1 MII Interface

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.5 Programming6.5.1 ArchitectureThis section describes the opera

Pagina 34 - 6.4.2 Reduced MII Interface

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com3 Device ComparisonTable 3-1. Device Features ComparisonDEVICE TE

Pagina 35

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 6-6. 4B5B Code-Group Encoding/DecodingDATA CODES0 11110 000

Pagina 36 - 6.4.5 PHY Address

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.5.1.1.2 ScramblerThe scrambler is required to control the radia

Pagina 37

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.5.1.2.1 Analog Front EndIn addition to the Digital Equalization

Pagina 38 - 6.4.7 Reset Operation

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015In order to ensure quality transmission when employing MLT-3 enco

Pagina 39 - 6.5.1 Architecture

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comThe DP83848VYB is completely ANSI TP-PMD compliant and includes B

Pagina 40

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015In order to maintain synchronization, the descrambler must contin

Pagina 41 - Detailed Description 41

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.5.1.3.1.1 Half Duplex ModeIn Half Duplex mode the DP83848VYB fu

Pagina 42

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015When heartbeat is enabled, approximately 1 µs after the transmiss

Pagina 43 - Detailed Description 43

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.5.1.3.9 TransmitterThe encoder begins operation when the Transm

Pagina 44 - UD = (SD ⊕ N) (2)

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-8. Register TableRegister Name Addr Tag Bit 15 Bit 14 Bit

Pagina 45 - Detailed Description 45

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20154.1 Pin LayoutPTB Package48-Pin HLQFPTop ViewCopyright © 2007–201

Pagina 46

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 6-8. Register Table (continued)Register Name Addr Tag Bit 1

Pagina 47 - Detailed Description 47

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.6.1.1 Register DefinitionIn the register definitions under the

Pagina 48 - 6.6.1 Register Block

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 6-9. Basic Mode Control Register (BMCR), address 0x00h (con

Pagina 49 - Table 6-8. Register Table

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-10. Basic Mode Status Register (BMSR), address 0x01h (con

Pagina 50

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 6-13. Negotiation Advertisement Register (ANAR), address 0x

Pagina 51

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-13. Negotiation Advertisement Register (ANAR), address 0x

Pagina 52

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.6.1.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR)

Pagina 53

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.6.1.1.8 Auto-Negotiate Expansion Register (ANER)This register c

Pagina 54

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 6-17. Auto-Negotiation Next Page Transmit Register (ANNPTR)

Pagina 55

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-18. PHY Status Register (PHYSTS), address 10h (continued)

Pagina 56

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com4.2 Package Pin AssignmentsVBH48A PIN # PIN NAME VBH48A PIN # PIN

Pagina 57

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.6.1.2.2 MII Interrupt Control Register (MICR)This register impl

Pagina 58

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-20. MII Interrupt Status and Misc. Control Register (MISR

Pagina 59

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.6.1.2.6 100 Mb/s PCS Configuration and Status Register (PCSR)Th

Pagina 60

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.6.1.2.7 RMII and Bypass Register (RBR)This register configures

Pagina 61

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com6.6.1.2.9 PHY Control Register (PHYCR)This register provides cont

Pagina 62

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Table 6-26. PHY Control Register (PHYCR), address 0x19h (continue

Pagina 63

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 6-27. 10Base-T Status/Control Register (10BTSCR), address 1

Pagina 64

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20156.6.1.2.12 Energy Detect Control (EDCR)This register provides con

Pagina 65

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com7 Application, Implementation, and LayoutNOTEInformation in the f

Pagina 66

1:11:1RJ45NOTE: CENTER TAP IS PULLED TO VDD*PLACE CAPACITORS CLOSE TO THETRANSFORMER CENTER TAPSRD-RD+TD-TD+0.1 PF*0.1 PF*COMMON MODE CHOKESMAY BE REQ

Pagina 67

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015SIGNAL TYPE PIN # DESCRIPTIONNAMETXD_0 I 3 MII TRANSMIT DATA: Tra

Pagina 68 - 7.2.1 Design Requirements

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comFigure 7-3. Crystal Oscillator CircuitTable 7-1. 25-MHz Oscillato

Pagina 69

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015Figure 7-4. Power Feedback Connection7.2.1.3.1 Power Down and Int

Pagina 70

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.comTable 7-4. Magnetics RequirementsPARAMETER TYP UNITS CONDITIONTur

Pagina 71

Zo= F60¥ErGln F1.98 ×l2 × H + T0.8 × W + TpG Zo= F87¥Er+ (1.41)Glnl5.98H0.8 W + Tp DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 200

Pagina 72

Zdiff= 2 × ZoF1 [email protected] Zdiff= 2 × Zo× F1 [email protected] DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www

Pagina 73

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20157.2.3 Application CurvesFigure 7-9. Sample 100 Mb/s Waveform (MLT

Pagina 74

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com7.3 Layout7.3.1 Layout Guidelines7.3.1.1 PCB Layout Consideration

Pagina 75 - 7.2.3 Application Curves

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20157.3.1.2 PCB Layer StackingTo meet signal integrity and performanc

Pagina 76 - 7.3.1 Layout Guidelines

PHYComponentOptional 0 : or BeadGround PinVdd PinPCB ViaVddPCBVia0.1 PFPlane Coupling ComponentPHY Component Note:Power/ Ground Planes Voided under

Pagina 77

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 20158 Device and Documentation Support8.1 Documentation Support8.1.1

Pagina 78 - 7.3.2 Layout Example

DP83848C,DP83848IDP83848VYB, DP83848YBSNLS266E –MAY 2007–REVISED MARCH 2015www.ti.com4.6 LED InterfaceSee Table 6-2 for LED Mode Selection.SIGNAL NAME

Pagina 79

PACKAGE OPTION ADDENDUMwww.ti.com10-Sep-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

Pagina 80 - PACKAGE OPTION ADDENDUM

PACKAGE OPTION ADDENDUMwww.ti.com10-Sep-2014Addendum-Page 2

Pagina 81

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

Pagina 82 - IMPORTANT NOTICE

DP83848C,DP83848IDP83848VYB, DP83848YBwww.ti.comSNLS266E –MAY 2007–REVISED MARCH 2015SIGNAL NAME TYPE PIN # DESCRIPTIONPHYAD0 (COL) S, O, PU 42 PHY AD

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