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DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com3.9 10 Mb/s and 100 Mb/s PMD InterfaceSIGNAL NAME TYPE PIN DESCRIPTIONNO.TD-, TD+ I/O 14 D

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20154 Specifications4.1 Absolute Maximum Ratings(1)(2)MIN MAX UNITSupply Voltage (VCC) –0.5 4.

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com4.5 Electrical Characteristics: DCPINPARAMETER TEST CONDITIONS MIN TYP MAX UNITTYPESVIHI,I

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20154.6 Electrical Characteristics: ACPARAMETER DESCRIPTION NOTES MIN TYP MAX UNITPOWER UP TIM

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comElectrical Characteristics: AC (continued)PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT100B

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Electrical Characteristics: AC (continued)PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT10-M

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comElectrical Characteristics: AC (continued)PARAMETER DESCRIPTION NOTES MIN TYP MAX UNITISOL

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Figure 4-2. Reset TimingFigure 4-3. MII Serial Management TimingFigure 4-4. 100 Mb/s MII T

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFigure 4-5. 100 Mb/s MII Receive TimingFigure 4-6. 100BASE-TX MII Transmit Packet Latency

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Figure 4-8. 100BASE-TX Transmit Timing (tR/Fand Jitter)Figure 4-9. 100BASE-TX Receive Pack

MII/RMII INTERFACE10BASE -T&100BASE-TXTRANSMIT BLOCK10BASE -T&100BASE-TXRECEIVE BLOCKMANAGEMENT REGISTERSAUTO-NEGOTIATIONREGISTERSCLOCKGENERAT

T2.17.1T2.17.2T2.17.31 0 1 0 1 0 1 0 1 0 1 11st SFD Bit Decoded0000 Preamble SFD DataRXD[3:0]RX_DVRX_CLKCRSTPRDrT2.15.1T2.15.2TX_CLKTX_ENTXDPMD Output

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Figure 4-16. 10BASE-T Receive Timing (End of Packet)Figure 4-17. 10-Mb/s Heartbeat TimingF

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFigure 4-21. 100BASE-TX Signal Detect TimingFigure 4-22. 100-Mb/s Internal Loopback Timing

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Figure 4-23. 10-Mb/s Internal Loopback TimingFigure 4-24. RMII Transmit TimingFigure 4-25.

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFigure 4-26. Isolation TimingFigure 4-27. 25 MHz_OUT TimingFigure 4-28. 100-Mb/s X1 to TX_

MII/RMII INTERFACE10BASE -T&100BASE-TXTRANSMIT BLOCK10BASE -T&100BASE-TXRECEIVE BLOCKMANAGEMENT REGISTERSAUTO-NEGOTIATIONREGISTERSCLOCKGENERAT

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.3 Feature Description5.3.1 Auto-NegotiationThe Auto-Negotiation function provides a mech

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015The BMSR also provides status on:• Whether or not Auto-Negotiation is complete• Whether or

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.3.1.6 Auto-Negotiation Complete TimeParallel detection and Auto-Negotiation take approxi

VCC165:2.2 k:AN0 = 1LED_LINKDP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Specifically, when the LED output is used to drive the LED dir

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Table of Contents1 Device Overview ... 1 4.5 Electri

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFor transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.4.1.2 Collision DetectFor Half Duplex, a 10BASE-T or 100BASE-TX collision is detected wh

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comThe elasticity buffer will force Frame Check Sequence errors for packets which overrun or

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Turnaround is defined as an idle bit time inserted between the Register Address field and

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.4.4 PHY AddressThe 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL p

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015The DP83848Q-Q1 can Auto-Negotiate or parallel detect to a specific technology depending o

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.5 Programming5.5.1 ArchitectureThis section describes the operations within each transce

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Table 5-6. 4B5B Code-Group Encoding/DecodingDATA CODES0 11110 00001 01001 00012 10100 0010

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.5.1.1.2 ScramblerThe scrambler is required to control the radiated emissions at the medi

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.5.1.2.1 Analog Front EndIn addition to the Digital Equalization and Gain Control, the DP

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com3 Pin Configuration and FunctionsThe DP83848Q-Q1 pins are classified into the following in

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comThe DP83848Q-Q1 uses an extremely robust equalization scheme referred as ‘Digital Adaptive

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015The digital oscilloscope plot provided in Figure 5-9 illustrates the severity of the BLW e

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.5.1.2.9 4B/5B DecoderThe code-group decoder functions as a look up table that translates

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015The signal at the start of a packet is checked by the smart squelch and any pulses not exc

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.5.1.3.4 Carrier SenseCarrier Sense (CRS) may be asserted due to receive activity once va

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.5.1.3.10 ReceiverThe decoder detects the end of a frame when no additional mid-bit trans

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comTable 5-8. Register TableRegister Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Table 5-8. Register Table (continued)Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bi

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.6.1 Register DefinitionIn the register definitions under the ‘Default’ heading, the foll

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Table 5-9. Basic Mode Control Register (BMCR), address 0x00h (continued)BIT BIT NAME DEFAU

TOP VIEW(not to scale)DAP = GNDIOGNDRXD_3/PHYAD4RXD_2/PHYAD3RXD_1/PHYAD2RXD_0/PHYAD1COL/PHYAD0RX_ER/MDIX_ENCRS/CRS_DV/LED_CFGRX_DV/MII_MODERX_CLKPFBIN

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comTable 5-10. Basic Mode Status Register (BMSR), address 0x01h (continued)BIT BIT NAME DEFAU

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.6.1.5 Auto-Negotiation Advertisement Register (ANAR)This register contains the advertise

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)This register c

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)Table 5-15. Aut

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)This register contains the ne

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.6.2 Extended Registers5.6.2.1 PHY Status Register (PHYSTS)This register provides a singl

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comTable 5-18. PHY Status Register (PHYSTS), address 10h (continued)BIT BIT NAME DEFAULT DESC

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.6.2.3 Receiver Error Counter Register (RECR)This counter provides information required t

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.6.2.5 RMII and Bypass Register (RBR)This register configures the RMII Mode of operation.

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.6.2.7 PHY Control Register (PHYCR)This register provides control for Phy functions such

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com3.2 Package Pin AssignmentsPIN NO. PIN NAME1 IO_VDD2 TX_CLK3 TX_EN4 TXD_05 TXD_16 TXD_27 T

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comTable 5-24. PHY Control Register (PHYCR), address 0x19h (continued)BIT BIT NAME DEFAULT DE

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20155.6.2.9 CD Test and BIST Extensions Register (CDCTRL1)This register controls test modes fo

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com5.6.2.10 Energy Detect Control (EDCR)This register provides control and status for the Ene

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20156 Application and ImplementationNOTEInformation in the following applications sections is

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFigure 6-2. 10/100-Mb/s Twisted-Pair Interface6.2.1.2 Clock IN (X1) RequirementsThe DP8384

Pin 19 (PFBOUT)Pin 16 (PFBIN1)Pin 30 (PFBIN2)10 PF0.1 PF0.1 PF0.1 PF+-DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Table 6-1. 25-MHz Os

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com6.2.1.4 MagneticsThe magnetics have a large impact on the PHY performance as well. While s

S0.96Hdiff oZ 2Z (1 0.48(e )æ ö-ç ÷è ø= -or60 2H TZ ln 1.980.8W TEæ ö+æ öç ÷=ç ÷ç ÷+è øè øor87 HZ ln 5.980.8W TE (1.41)æ öæ öç ÷=ç ÷ç ÷++è øè øDP83848

S2.9Hdiff oZ 2Z (1 0.347(e )æ ö-ç ÷è ø= -DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFigure 6-7. Microstrip Impedance - DifferentialSt

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20157 Power Supply RecommendationsThe device Vdd supply pins should be bypassed with low imped

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20153.3 Serial Management InterfaceSIGNALTYPE PIN NO. DESCRIPTIONNAMEMDC I 25 MANAGEMENT DATA

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com8 Layout8.1 Layout Guidelines8.1.1 PCB Layout ConsiderationsPlace the 49.9-Ω,1% resistors,

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 2015Figure 8-3. PCB Stripline Layer StackingWithin a PCB it may be desirable to run traces usi

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.comFigure 8-4. Alternative PCB Stripline Layer Stacking72 Layout Copyright © 2011–2015, Texas

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20158.2 Layout ExampleFigure 8-5. Layout ExampleCopyright © 2011–2015, Texas Instruments Incor

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com9 Device and Documentation Support9.1 Documentation Support9.1.1 Related Documentation• AN

PACKAGE OPTION ADDENDUMwww.ti.com8-Sep-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEco

PACKAGE OPTION ADDENDUMwww.ti.com8-Sep-2014Addendum-Page 2continues to take reasonable steps to provide representative and accurate information but ma

TAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W

*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)DP83848QSQ/NOPB WQFN RTA 40 1000 367.0 367.0

www.ti.comPACKAGE OUTLINECSEE TERMINALDETAIL40X 0.30.2 4.6 0.140X 0.50.30.8 MAX(0.1) TYP0.050.0036X 0.54X4.5A6.15.9B6.15.90.50.30.30.2WQFN - 0.8 mm m

DP83848Q-Q1SNLS341C –MARCH 2011–REVISED MARCH 2015www.ti.com3.5 Clock InterfaceSIGNAL TYPE PIN NO. DESCRIPTIONNAMEX1 I 28 CRYSTAL/OSCILLATOR INPUT: Th

www.ti.comEXAMPLE BOARD LAYOUT0.07 MINALL AROUND0.07 MAXALL AROUND40X (0.25)40X (0.6)( ) TYPVIA0.236X (0.5)(5.8)(5.8)( 4.6)(R ) TYP0.05(0.74)TYP(1.48)

www.ti.comEXAMPLE STENCIL DESIGN40X (0.6)40X (0.25)36X (0.5)(5.8)(5.8)9X ( 1.28)(1.48)TYP(R ) TYP0.05(1.48) TYPWQFN - 0.8 mm max heightRTA0040APLASTIC

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

DP83848Q-Q1www.ti.comSNLS341C –MARCH 2011–REVISED MARCH 20153.8 Strap OptionsThe DP83848Q-Q1 uses many of the functional pins as strap options. The va